1. Technical Field
The embodiments described herein relate to semiconductor integrated circuits, and in particular, clock test apparatus and methods for determining an internal clock signal delay.
2. Related Art
Generally, a semiconductor integrated circuit, such as an SDRAM (Synchronous Dynamic Random Access Memory), uses an external clock signal to control the operation of the circuit. The external clock signal is often used to generate a data output clock signal within the circuit, and the data output clock signal often controls the operation of a data output buffer. It will also be understood that other internal clock signals can be generated based on such an external clock signal.
Such an internal clock signal is often delayed from relative to the external clock signal due to delay introduced by, e.g., a clock input buffer and individual transmission lines within the circuit. Thus, the interval clock signal is often out of phase with the external clock signal. When the internal clock and the external clock are out of phase, the circuits operational speed can be reduced, and at worst, a data output operation may not performed. In order to solve this problem, conventional circuits often use a DLL (Delay Locked Loop) circuit or a PLL (Phase Locked Loop) circuit to correct the delay of the internal clock relative to the external clock.
At present, however, even if the delay is corrected, it may not be possible to test the data output operation while in a wafer state. Accordingly, the data output operation is often tested after the package process to determine a difference in phase between the internal clock and the external clock. At this stage, however, it is too late to fix the circuit and the circuit cannot be used if in fact their is a problem. This lowers yields and obviously increases costs.